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Packaging Central

Packaging Highlights

EDA and the Heterogeneous Integration Roadmap (3D InCites; Jun 3, 2020)

IFTLE 451: Advanced Packaging is Leading Electronics into the 2020s (3D InCites; Jun 1, 2020)

Modeling, Simulation and Test for Multi-die IC Designs (3D InCites; May 27, 2020)

ASMPT well positioned to ride the next wave of Advanced Packaging in Heterogeneous Integration (DigiTimes; May 26, 2020)

Fan-Out Wafer-Level Packaging And Copper Electrodeposition (Semiconductor Engineering; May 21, 2020)

IFTLE 450: Chiplet is the New Buzzword but Disintegration is the New Technology (3D InCites; May 20, 2020)

Building 3D neural structures on a single wafer (EE Times; May 19, 2020)

IFTLE 449: Advanced Packaging and Chiplets at the IMAPS DPC (3D InCites; May 13, 2020)

An Inside Look At Testing’s Leading Edge (Semiconductor Engineering; May 12, 2020)

Temporary Wafer Bonding System Is Based On Electrostatics, Not Adhesives (3D InCites; May 11, 2020)

Chiplets: The New Era Begins (3D InCites; May 8, 2020)

System-on-Chip Disintegration is Underway (3D InCites; May 7, 2020)

Ask the Expert: Q&A with Process Engineers (EE Times Asia; May 5, 2020)

Wanted: Process Engineers Versed in Packaging (EE Times; May 4, 2020)

SemiSister Success Story: A Woman on the Edge of 3D Technology (3D InCites; May 1, 2020)

The Morphing of Electronic Product Design in the Era of Moore’s Law 2.0 (Embedded Computing Design; Apr 20, 2020)

Apple supplier Foxconn steps up semiconductor plans with deal to build a new base in Qingdao (South China Morning Post; Apr 17, 2020)

Hon Hai reportedly to build IC packaging, testing plant in China (Focus Taiwan; Apr 16, 2020)

The Story Behind Advanced Packaging, Heterogeneous Integration And Test (Semiconductor Engineering; Apr 6, 2020)

Adding New Dimensions to Power Electronics Packaging (Electronic Design; Apr 3, 2020)

How does heterogeneous integration impact sensors? (EE World Online; Mar 26, 2020)

IFTLE 444: Chip on Interposer on Substrate vs High Density Chips-Last Package Cost Modeling (3D InCites; Mar 26, 2020)

IFTLE 443: Controlling Warpage and Placement Error for FOWLP (3D InCites; Mar 23, 2020)

The Golden Age of Packaging Brought to you by Chiplet Integration (3D InCites; Mar 16, 2020)

An Inside Look at 3D-DfT Standard IEEE Std 1838™-2019 (3D InCites; Mar 17, 2020)

Heterogeneous Integration Technologies for Moore’s Law 2.0 and Beyond (3D InCites; Mar 12, 2020)

Grading Chips For Longer Lifetimes (Semiconductor Engineering; Mar 10, 2020)

Wafer Test Challenges For Chiplets (Semiconductor Engineering; Mar 10, 2020)

Comprehensive review of heterogeneously integrated 2-D materials (; Mar 6, 2020)

3nm: Blurring Lines Between SoCs, PCBs And Packages (Semiconductor Engineering; Mar 2, 2020)

Chiplet Momentum Rising (Semiconductor Engineering; Feb 26, 2020)

Is The HIR the Best Path to Increased Revenues? (3D InCites; Feb 25, 2020)

IFTLE 441: Will TSMC Ever Put a Chip or Packaging Facility in the USA? (3D InCites; Feb 21, 2020)

Big Data, Speed and Security Dominate DesignCon 2020 (3D InCites; Feb 12, 2020)

IFTLE 440: Copper Pillar Bump Development for 7nm Node Devices (3D InCites; Feb 10, 2020)

Researchers demonstrate ultra-flexible heterogeneous electronics (eeNews Europe; Feb 6, 2020)

SiP and Heterogeneous Integration as Key Driving Force of Growth for IC Packaging and Testing (CTIMES; Feb 3, 2020)

IFTLE 439: imec’s Flip Chip on FOWLP… a Closer Look (3D InCites; Jan 31, 2020)

Is This The Year Of The Chiplet? (Semiconductor Engineering; Jan 23, 2020)

IFTLE 438: Reliability Test For 0.3mm WLCSP; Copper RDL Trace Requirements (3D InCites; Jan 21, 2020)

Novel Multi-die Integration Concept Offers Big Benefits (3D InCites; Jan 14, 2020)

IFTLE 437: Packaging Trends for Artificial Intelligence (3D InCites; Jan 13, 2020)

SJSemi strengthens presence in wafer-level 3D packaging segment (DigiTimes; Jan 3, 2020)

Advanced Packaging is Everyone’s Business! (3D InCites; Dec 13, 2019)

IFTLE 434: Process Optimization for a Reliable NXP FOWLP Microcontroller (3D InCites; Dec 12, 2019)

IC buyers will purchase more chips housed in advanced semiconductor packages (Electronics Sourcing Online; Dec 5, 2019)

IFTLE 433: AMD Chiplets go Commercial Amidst a Need for Chiplet Standardization (3D InCites; Dec 5, 2019)

Vehicle Autonomy & Electrification Push Advanced Packaging for Automotive Applications (3D InCites; Dec 4, 2019)

Talking about Neural Networks and SoC Design Challenges (3D InCites; Dec 4, 2019)

Thermal Challenges In Advanced Packaging (Semiconductor Engineering; Dec 2, 2019)

EU Project Sets Sights on Advanced Packaging (EE Times Europe Nov 26, 2019)

Powering future optical microsystems with chip-scale integrated photonics (Nanowerk; Nov 25, 2019)

Boosting the 5G Network (Labroot; Nov 24, 2019)

SEMICON Europa and Productronica 2019 Exhibitor Showcase (Nov 21, 2019)

PTI chair sees FOPLP as alternative solution for IC scaling (DigiTimes; Nov 21, 2019)

IFTLE 431: Samsung Qualifies EDA Tools for Multi-die Integration (3D InCites; Nov 17, 2019)

Highlights of the day: TSMC, UMC to give driver IC designers more capacity support (DigiTimes; Nov 14, 2019)

Fujian, Hong Kong sign joint 5.4 billion yuan investment deal (China Daily; Nov 14, 2019)

SEMI 3D & Systems Summit to Spotlight Latest in 3D Roadmap, Heterogeneous Integration and SiP Technologies (3D InCites; Nov 11, 2019)

IFTLE 430: Exascale Computing in Europe: Leading Edge Packaging is the Key! (3D InCites; Nov 11, 2019)

3D VLSI Open Workshop Showcases 3D IC Supply Chain Capabilities (3D InCites; Nov 8, 2019)

Die attach equipment: Yole’s analysts announce a consolidation of the market (3D InCites; Nov 4. 3019)

The IWLPC Fan-out PLP Smack Down (3D InCites; Oct 31, 2019)

ASE eyes bright 1Q20 amid strong 5G-driven backend demand (DigiTimes; Oct 31, 2019)

Heterogeneous Integration ramps up electronics clout (Evaluation Engineering; Oct 28, 2019)

IFTLE 429: Samsung 12-layer memory with 3D-TSV; SHIP Winners (3D InCites; Oct 24, 2019)

Keeping an Eye on the Future (POTs and PANs; Oct 22, 2019)

Research Seeks to Improve Computers’ Energy Efficiency on Micro, Macro Levels (I-Connect007; Oct 21, 2019)

What’s The Best Advanced Packaging Option? (Semiconductor Engineering; Oct 17, 2019)

IFTLE 428: Panel Level Processing: We’ve Come A Long Way Baby! (3D InCites: Oct 16, 2019)

IWLPC 2019 Brings You Advanced Packaging in an Interconnected World (3D InCites; Oct 14, 2019)

Highlights from EDPS 2019 (3D InCites; Oct 14, 2019)

Samsung Electronics Develops Most Advanced Semiconductor Packaging Technology (Business Korea; Oct 9, 2019)

More Data, More Processing, More Chips (Semiconductor Engineering; Oct 7, 2019)

Reaping the Benefits of a Design and Manufacturing Ecosystem (3D InCites; Oct 4, 2019)

IFTLE 127: TSMC’s Next-Gen 3D Technology  (3D InCites; Oct 4, 2019)

Exhibitor Highlights at IMAPS International Symposium (3D InCites; Sep 26, 2019)

IFTLE 426: Exascale Computing is Near; Incandescent Lightbulbs get a Reprieve (3D InCites; Sep 26, 2019)

Is Fan-Out packaging still popular? (AnySilicon; Sep 24, 2019)

Driving With Chiplets (Semiconductor Engineering; Sep 24, 2019)

Making more of Moore’s Law (Evaluation Engineering; Sep 23, 2019)

The Race To Next-Gen 2.5D/3D Packages (Semiconductor Engineering; Sep 23, 2019)

Stacking Memory On Logic, Take Two (Semiconductor Engineering; Sep 19, 2019)

Is Fan-Out packaging still popular? Equipment & material companies are the heartbeats of this ecosystem (3D InCites; Sep 17, 2019)

IFTLE 425: Deca FOWLP is Going Mainstream; Highlights from Hot Chips (3D InCites; Sep 11, 2019)

EPS 2019: Imagining Thomas Edison as the Father of Advanced Packaging (3D InCites; Sep 10, 2019)

New Technologies To Support 3D-ICs (Semiconductor Engineering; Sep 4, 2019)

Advanced Packaging Options Increase (Semiconductor Engineering; Aug 19, 2019)

IFTLE  423: GLOBALFOUNDRIES and ARM Turn to 3D Chip Stacks for High Performance Computing (3D InCites; Aug 19, 2019)

ASE to buy new factory building to optimize capacity deployment (DigiTimes; Aug 13, 2019)

IFTLE 422: Is Advanced Packaging Production Returning to the US by SHIP? (3D InCites; Aug 9, 2019)

A Look Inside The 3D Technology Toolbox For STCO (3D InCites; Aug 8, 2019)

Intel Shows Off Chip Packaging Powers (IEEE Spectrum; Jul 31, 2019)

New Details About More-than-Moore Test Technology Advances (3D InCites; Jul 31, 2019)

IFTLE 421: Intel Showcases Co-EMIB Advanced Packaging Architecture (3D InCites; Jul 30, 2019)

Memory Dominates Semiconductors, Driving Packaging (Forbes; Jul 21, 2019)

Chip Stacks Hit Semicon Spotlight (EE Times; Jul 12, 2019)

Intel unveils new 3D chip packaging design (Network World; Jul 10, 2019)

SiP Technology To Enable Technology Megatrends (3D InCites; Jul 2, 2019)

Good News about Glass Substrates (3D InCites; Jun 24, 2019)

IFTLE 417: Passing the Advanced Packaging Baton to TSMC’s 3D-MiM (3D InCites; Jun 20, 2019)

What’s Next In Advanced Packaging (Semiconductor Engineering; Jun 20, 2019)

Power, Reliability And Security In Packaging (Semiconductor Engineering; Jun 19, 2019)

Fan-out Panel-level Packaging Comes to the ECTC Technology Corner (3D InCites; Jun 12, 2019)

ECTC Packaging Trends (Semiconductor Engineering; Jun 10, 2019)

Moore’s Law is Dead (Again), Chiplets are Hot, and other Highlights of ECTC 2019 (3D InCites; Jun 4, 2019)

IFTLE 415:Substrate-like PCBs; Three Top Ten Packaging Houses are China-based (3D InCites; Jun 1, 2019)

Asian Edge: The big advance of the Chinese IC packaging and testing industry (DIGITIMES, May 15, 2019)

Chiplet Momentum Builds, Despite Tradeoffs (Semiconductor Engineering; May 13, 2019)

U2U 2019 Conference Dives into 2.5/3D IC Design (3D InCites; May 13, 2019)

IFTLE 413: Beware of Technology Hype for the Automotive Market (3D InCites; May 10, 2019)

ITFLE 412: Samsung Discusses Packaging for the 4th Industrial Revolution; Yole looks at Non-TSV Options (3D InCites; May 6, 2019)

ECTC 2019 Will Go Back to Basics to Plan for the Future of Microelectronics and Packaging (3D InCites; May 6, 2019)

IFTLE 411: Focus on the Sensor Technology Market (3D InCites; Apr 25, 2019)

Inspecting IC Packages Using Die Sorters (Semiconductor Engineering; Apr 18, 2019)

Moore’s Law Now Requires Advanced Packaging (Semiconductor Engineering; Apr 18, 2019)

Update on 3D X-ray and DBI Technology for Advanced and 3D Packaging (3D InCites; Apr 16, 2019)

IFTLE 410: ST Microelectronics Bets on SiC; A Look at Power Device Packaging (3D InCites; Apr 15, 2019)

Advanced Packaging Bringing Semiconductor Revolution (eeDesignIT; Apr 8, 2019)


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